SystemVerilog. Unified Hardware Design, Specification, and Verification Language

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

19-08-2021

Publisher

British Standards Institution

Committee	EPL/501
DocumentType	Standard
Pages	1320
PublisherName	British Standards Institution
Status	Current
Supersedes	BS IEC 62530:2011

This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.